
157
7593L–AVR–09/12
AT90USB64/128
Table 16-2 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-
for more details.
Table 16-3 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor-
rect PWM mode.
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-
Bits 5:4 – COM2B1:0: Compare Match Output B mode
These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0
bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin
must be set in order to enable the output driver.
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the
WGM22:0 bit setting.
Table 16-4 shows the COM2B1:0 bit functionality when the WGM22:0 bits
are set to a normal or CTC mode (non-PWM).
Table 16-2.
Compare Output mode, fast PWM mode
(1).
COM2A1
COM2A0
Description
0
Normal port operation, OC2A disconnected
01
WGM22 = 0: Normal Port Operation, OC0A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
1
0
Clear OC2A on Compare Match, set OC2A at TOP
1
Set OC2A on Compare Match, clear OC2A at TOP
Table 16-3.
Compare Output mode, phase correct PWM mode
COM2A1
COM2A0
Description
0
Normal port operation, OC2A disconnected
01
WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
10
Clear OC2A on Compare Match when up-counting. Set OC2A on Compare
Match when down-counting.
11
Set OC2A on Compare Match when up-counting. Clear OC2A on Compare
Match when down-counting.
Table 16-4.
Compare Output mode, non-PWM mode.
COM2B1
COM2B0
Description
0
Normal port operation, OC2B disconnected
0
1
Toggle OC2B on Compare Match
1
0
Clear OC2B on Compare Match
1
Set OC2B on Compare Match